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| ADC180 Programmable Integrating A/D Converter THALER CORPORATION. Represented by: Rhopoint Components Ltd. www.rhopointcomponents.com FEATURES * 26 BIT RESOLUTION * UP TO 2.5kHz CONVERSION RATES * AUTO ZERO FUNCTION * 10.48 V INPUT RANGE * 0.5ppm/C MAX. SCALE FACTOR ERROR AND 2 ppm MAX. LINEARITY ERROR (-55C to +125C). * 8 BIT PARALLEL DATA BUS * INTERNAL CRYSTAL CLOCK and PRECISION REFERENCE * LOW POWER CONSUMPTION: 0.4 WATTS APPLICATIONS * INERTIAL GUIDANCE * TEST EQUIPMENT * DATA ACQUISITION * SCIENTIFIC INSTRUMENTS * MEDICAL INSTRUMENTS * WEIGHT SCALES DESCRIPTION The ADC180 is a 26 bit, charge balanced A/D converter. Continuous sampling of 20 MHz and conversion rates of up to 2.5 kHz make the converter ideal for low frequency signal measurement. The integration time is user selectable through an external capacitor. The ADC180 will continuously collect and average integrations until the user requests data. Converter resolution is dependent on the number of integration cycles completed before the data is requested. Converter resolution ranges from 13 - 26 bits. In order to retain accuracy, internal calculations are made at a 32 bit level. The output of the result is also made at the 32 bit level. This makes it possible to use a relatively high conversion rate and average the data external to the converter without loss of accuracy due to computation roundoff errors. For inertial guidance systems, velocity information can be obtained at a high rate without loss of position accuracy. The use of hybrid technology allows for separation of sensitive analog circuitry from digital circuit noise. This produces far superior accuracy over monolithic A/D convertors. The converter uses a proprietary, patented charge balance modulator. It has an internal crystal clock, microcontroller, precision reference, and patented nonlinear temperature compensation network which provides excellent electrical performance over temperature. The maximum scale factor drift is 0.5ppm/oC, maximum offset drift of 0.1ppm/oC, and a maximum nonlinearity over the mil. temp. range of 2 ppm. The ADC180 is packaged in a 40 pin hermetic TDIP and requires 15V and +5V supplies. The converter dissipates 450 mW and is available in commercial and military grades. ADC180DS REV I FEB 05 ELECTRICAL SPECIFICATIONS MODEL PARAMETER ACCURACY Resolution Input Equivalent Noise Offset without Auto Zero Offset with Auto Zero Scale Factor Error Noise (.1-10Hz) @ 10V Nonlinearity Normal Mode Rejection(1) Common Mode Rejection TEMPERATURE STABILITY Offset Full Scale TIME STABILITY Offset Full Scale (2) ERROR ALL SOURCES 24 hrs, +/- 1 Deg. C Amb. 90 days, +/- 5 Deg. C Amb. 1 year, +/- 5 Deg. C Amb. CONVERSION TIME WARM-UP TIME POWER SUPPLY REJECTION +Vcc, -Vee 5 VDC Input Range Bias Current Input Impedance Max. Input Voltage 80 80 -10.485760 1.2 200 -Vee 0.250 .0005, 2 .0010, 2 .0015, 2 3200 5 0.1 2 0.2 1.0 13 .25 4 1 100 6 1 60 80 2 26 MIN ADC180C TYP MAX (Vcc = +15V, Vee = -15V, Vdd = + 5V, TA = +25oC) ADC180 ADC180M ADC180CA MIN * * 2 0.5 50 * * * * 0.1 0.5 * * * TYP MAX * MIN * TYP MAX * bits V ppm FS ppm FS ppm FS Vpp ppm FS dB dB ppm/o C ppm/o C ppm/month ppm/24 hrs. * * * * * * * * * * * * * .0003, 2 .0008, 2 .0013, 2 * * * * * * * * * %, +/- counts %, +/- counts %, +/- counts ms minutes * * +10.485755 3 +Vcc * * dB dB V nA G V ANALOG INPUT CHARACTERISTICS * * * * * * * * * * * * POWER SUPPLY VOLTAGES +Vcc -Vee +Vdd POWER SUPPLY CURRENTS +Vcc -Vee +Vdd DIGITAL INPUTS Low High DIGITAL OUTPUTS Low High TEMPERATURE RANGE * Same as ADC180C Notes: 1) 60 Cycle 0.8 4.0 -25 85 * * * * * -55 * 125 V V o +14.5 -14.5 +4.5 +15 -15 +5 23 24 42 +15.5 -15.5 +5.5 * * * * * * * * * * * * * * * * * * * * * * * * V V V mA mA mA V V 0.8 4.0 * * * * C 2) ( Max-Min Value) - Noise(0.1-10Hz) ADC180DS REV I FEB 05 THEORY OF OPERATION 34 35 Auto Zero Switch Vhi Vlow 39 3 Transadmittance Amplifier Charge Balance Modulator Duty Cycle Test Point 40 Crystal Clock 26 20MHz clock output Data Output 13 . . . 20 Output Buffer Microprocessor 21 29 22 23 24 Output Enable Auto Zero Data Request Status Lines FIGURE 1. BLOCK DIAGRAM The ADC180 uses a differential input to improve accuracy. To measure single source voltages, Vlow should be connected to the ground point of the source voltage to be measured. In figure 1, the switch is shown in the normal operating mode connecting Vhi and Vlow to the differential input of the transadmittance amplifier. For an autozero cycle, Vhi is disconnected and the input to the amplifier is shorted. The charge balance modulator (figure 2) uses a proprietary patented architecture to achieve the high accuracy of the ADC180 without any error correction method other than autozero. This enables the converter to sample the output of the transadmittance amplifier continuously at a sampling rate of 20 MHz. This is important for applications like inertial guidance systems where The conversion result between two consecutive data request inputs at times t1 and t2 is mathematically represented by the equation Viav = t2 1 t1 Vinp dt t2 - t1 The converter provides two 32 bit data words with the first word containing t2-t1 and the second word containing IIN t2 t1 Vinp dt t2 t1 Vinp dt Bidirectional Curent Source Bilevel Comparator must be measured without any loss of time increments. The output of the charge balance modulator is in the form of a pulse width modulation signal. The internal microprocessor provides all control functions and digital signal processing. The converter also has an internal crystal clock to avoid phase jitter errors and a tristate output buffer for easy interface with bus based systems. For the data output timing see figures 5 and 6. Direction Switch Data Output Figure 2. Patented Charge Balance Modulator ADC180DS REV I FEB 05 CONNECTING THE ADC180 DUTY CYCLE OUTPUT (pin 3) This logic level output allows monitoring of the integration cycle and is usually used for timing purposes. POWER SUPPLIES (pins 4-7) The ADC180 has internal 0.1F decoupling capacitors for all power supply inputs. This is sufficient for applications with relatively short power supply leads (approx. 5") or if additional capacitors are located on the circuit board. External capacitors of 10 F on the 15V inputs and 33 F on the +5V input is recommended for applications with longer power supply leads. GROUND (pin7) Since ground noise can result in a loss of accuracy, the ground connection should be made as solid as possible. Use of a ground plane is a good approach to maintain the full accuracy of the ADC180. OUTPUT DATA LINES (pins 13-20) The parallel output data is available on pins 13-20. Pin 20 is the Most Significant Bit and pin 13 the Least Significant Bit. The data lines go to a high impedance state when the Output Enable line is at a logic 1 level. ANALOG INPUTS (pins 39,40) The differential analog inputs are buffered by op amps and have a common mode rejection of approximately 80dB minimum. To maintain the full accuracy of the ADC180 it is recommended to maintain the input to analog low to less than 0.1VDC. To avoid differential noise pickup, parallel adjacent lines should be used for the analog inputs on PC boards and shielded lines outside of the PC connections. CAPACITOR (pin 34, 35) The only external component required to operate the ADC180 is a capacitor which sets the integration time. A 0.082F capacitor results in an integration time of approximately 250 s. For 2,000s a 0.68F capacitor is required. The relationship is linear for intermediate capacitor values. The main parameter affected by shorter conversion times is bias stability over temperature. Polystyrene, mylar, or polycarbonate capacitors are recommended. AUTO ZERO / RESET (pin 29) A logic 0 on this input will autozero the ADC180 by internally connecting the analog high to analog low. Since the internal microprocessor is reset, the ADC180 is not functional during this time (approximately 1s). S1 will go to logic 1 indicating that no data is available. After completing the autozero function, S1 will return to logic 0 and the ADC will begin collecting data. STATUS LINES (pins 23, 24) These lines indicate the present state of the ADC. After a data request has been received and the current integration cycle is complete, the ADC will output the data collected subsequent to the previous data request. S1 will go to logic 1 to acknowledge the data request. The 8 bytes of data will be placed on the data bus sequentially. A logic 1 on S0 indicates valid data on the data bus. After the data has been transmitted, S1 will return to logic 0. DATA REQUEST (pin 22) A logic 0 on this line initiates a data transfer sequence. OUTPUT ENABLE (pin 21) A logic 0 on this line enables outputs D0 - D7. (TOP VIEW) N.C. N.C. Duty Cycle Output Vee (-15V) Vcc (+15V) Vdd (+5V) GND N.C. N.C. N.C. N.C. N.C. D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 CAPACITOR 34 33 N.C. N.C. N.C. N.C. /AUTO ZERO / RESET N.C. N.C. N.C. N.C. S1 S0 /DATA REQUEST /OUTPUT ENABLE ANALOG LOW ANALOG HIGH N.C. N.C. N.C. ADC180 32 31 30 29 28 27 26 25 24 23 22 21 NC= Factory test points, do not connect to these pins. FIGURE 3. EXTERNAL CONNECTIONS ADC180DS REV I FEB 05 TIMING DIAGRAMS AutoZero tAZ * S0 * S1 * Data Request at logic 1, output enable (don't care) tTS tAC FIGURE 4. AUTO ZERO TIMING duty cycle tS1R /DR tNDR tDRA tDD S1 S0 enlarged detail data on D0 - D7 valid upon rising edge of S0 tDC S0 tDV D0 - D7 FIGURE 5. DATA REQUEST CYCLE TIMING SIGNAL AutoZero request Autozero Cycle port TriState time Data Request Acknowledge S1 Response after duty cycle Data Delay time before Next Data Request Data Valid Data Cycle SYMBOL tAZ tAC tTS tDRA tS1R tDD tNDR tDV tDC MIN 100 TYP MAX UNITS ns 1.3 30 * 27 50 0 1 2 * 34 s ms s s s s s * TDRA must be either 1 integration cycle minimum or until S1 goes high. FIGURE 6. TIMING TABLE ADC180DS REV I FEB 05 SPECIFICATIONS MAXIMUM RATINGS MODEL PARAMETER TEMPERATURE Operating Storage POWER SUPPLY Vcc Vee Vdd INPUTS analog inputs digital inputs MIN -55 0 +14 -14 +4 Vee 0 ADC180 MAX 125 150 +16 -16 +6 Vcc Vdd UNITS C C VDC VDC VDC ADC180 RESOLUTION (bits) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 LSB weighting (V) 0.31 0.62 1.25 2.5 5 10 20 40 80 160 320 640 1280 2560 Sampling Time (ms) approx. 3200 1600 800 400 200 100 50 25 12.5 6.25 3.12 1.56 0.78 0.39 Conversions Per Second 0.31 0.62 1.25 2.5 5 10 20 40 80 160 320 640 1280 2560 cycles w/0.082F cycles w/ 0.68F capacitor capacitor 12800 6400 3200 1600 800 400 200 100 50 25 13 6 3 1 1600 800 400 200 100 50 25 13 6 3 1 - Note: 0.082F external capacitor provides ~250s integration cycle 0.68F external capacitor provides ~2000s integration cycle FIGURE 7 APPROXIMATE SAMPLING TIME VS. RESOLUTION ADC180DS REV I FEB 05 outputword1 = (byte1 * 2^24) + (byte2 * 2^16) + (byte3 * 2^8) + byte4 outputword2 = ((byte5 - 8) * 2^24) + (byte6 * 2^16) + (byte7 * 2^8) + byte8 scales to 0V Vout = (outputword2 / outputword1) * 20 scales to 10V FIGURE 9 OUTPUT CALCULATION PSEUDO-CODE 40-PIN HYBRID PACKAGE INCHES DIM E D A L B2 B Q C P G1 B1 MIN 1.080 2.075 0.155 0.220 .100 typ .018 typ .015 .009 .012 .890 .040 typ .035 .012 .018 .910 MAX 1.100 2.115 0.185 0.240 NOTES: 1. GOLD PLATING 60 MICRO INCHES MINIMUM THICKNESS OVER 100 MICRO INCHES NOMINAL THICKNESS OF NICKEL FIGURE 10 MECHANICAL SPECIFICATIONS ADC180DS REV I FEB 05 |
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